1. Field of the Invention
This invention relates to a power amplifier with an idle current trimmed and a method of trimming the power amplifier.
2. Description of the Prior Art
A power amplifier for amplifying a signal with an idle current flowing through a field effect transistor trimmed and a method of trimming the idle current are known.
Such a prior art amplifier and method are disclosed in Japanese patent application provisional publication No. 8-125465. FIG. 8 is a circuit diagram of this prior art power amplifier. A variable resistor 44 is provided in the gate bias circuit 40 to adjust an idle current of an FET 30 to make the idle current even to eliminate a dispersion in the output power. This Japanese patent application also discloses a gate bias voltage generation circuit using a D/A converter. FIG. 9 is a block diagram of another prior art power amplifier including this gate bias voltage generation circuit. A D/A converter 70 supplies a gate bias voltage controlled in accordance with data in an EEPROM 60 under control of a CPU 50 using a negative supply voltage -V from a -V regulator 80.